1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device. In particular, the invention relates to a manufacturing method for a semiconductor device including a method of monitoring halfway through a manufacturing process of the semiconductor device and a method of reflecting monitoring information to its subsequent manufacturing process.
2. Description of the Related Art
Upon manufacturing any products, product-to-product variation (production variation) impairs uniformity in product characteristics (inclusive of function, performance, and shape). To prevent it, a manufacturer faces an agonizing choice between relaxing a production specification to keep a production yield at a certain level (decrease in quality) and complying with a product specification to thereby cause reduction in production yield (increase in cost). Under such circumstances, regarding a manufacturing method for a semiconductor device as a typical method for mass-production of goods as well, some improvement have been made and tried on a manufacturing method by combining a cost-oriented manufacturing method with a quality-oriented manufacturing method. Prior to explanation about the improved manufacturing method, generally-employed manufacturing methods for a semiconductor device are first described.
A semiconductor device is provided in a form of a semiconductor chip (for example, 0.5 mm in thickness, 10 mm in length, 8 mm in width) on which a number of electronic elements such as transistors, resistors, capacitors, diodes and wirings for electrically connecting the electronic elements together are formed, and the chip is housed in a package according to the environment it is actually used. The packaged chip is incorporated into an electronic device such as a computer, a mobile telephone, a game console, etc., for variety of use. A manufacturing process for semiconductor device consists of, as shown in a macro-manufacturing process flow of FIG. 2, a pre-manufacturing process X for lot-production of several dozens of wafers on which a number of semiconductor chips are assigned and a post-manufacturing process Y for separating the semiconductor chips assigned on the wafers from one another to be housed in packages and subjected to product testing. The post-manufacturing process Y hence includes package assembly and product testing. Electric characteristics of a semiconductor device are nearly determined at the time of placing the semiconductor chip on a wafer, in other words, upon the completion of the pre-manufacturing process X although there are a few exceptions, i.e., FPLD (digital IC), fuse memory, and such other semiconductor devices whose functions are determined by a user after the completion of the post-manufacturing process Y. It is assumed throughout the following description that characteristic variation due to the post-manufacturing process Y is negligible. In this specification, description of the manufacturing process for the semiconductor device is therefore exclusively focused on the pre-manufacturing process X. Description of the post-manufacturing process Y will accordingly be omitted hereafter.
Here, the pre-manufacturing process X for the semiconductor device will be described with reference to a typical and simplified manufacturing process flow of FIG. 3 in which basic processes are shown. A semiconductor device manufactured by utilizing these processes is also called a CMOS semiconductor device.
1. Field Oxide Film Formation
Insulating films partially different in thickness are selectively formed near the surfaces of a semiconductor substrate, in this example a P-type semiconductor substrate, through thermal oxidation etc. (FIG. 3, Step J).
2. N Well Formation
Phosphorous ions for N well formation are selectively implanted into the semiconductor substrate surface, for example, to thereby form an N well (FIG. 3, Step K).
3. Isolation with LOCOS
BF2 ions for P-type channel stopper formation are selectively implanted into the P-type semiconductor substrate surface and its vicinities, for example, after which an element isolation insulating film and channel stopper are selectively formed by using a LOCOS method etc. (FIG. 3, Step L).
4. Channel Doping
Phosphorous ions for controlling a threshold voltage are selectively implanted into the semiconductor substrate surface in an active region for element formation where a transistor is formed later to thereby form an impurity doped region (FIG. 3, Step M).
5. Gate Oxide Film Formation
An oxide film near the semiconductor substrate surface in the active region for element formation is removed to form a gate oxide film through thermal oxidation etc. (FIG. 3, Step N).
6. Polysilicon Gate Formation
A poly-crystalline silicon (polysilicon) gate is selectively formed on the gate oxide film through chemical vapor deposition (CVD), photolithography, and etching (FIG. 3, Step O).
7. Source/Drain Formation
After an oxide film is formed on the P-type semiconductor substrate surface by CVD or thermal oxidation, impurity-ions for forming source/drain (SD) regions are implanted to the polysilicon gate and the oxide film in desired regions of the active region for the element formation in a self-alignment manner to thereby form an N-type source region, an N-type drain region, a P-type source region, and a P-type drain region (FIG. 3, Step P).
8. Interlayer Insulating Film Formation
An oxide film is deposited on the P-type semiconductor substrate surface by CVD or the like to thereby form an interlayer insulating film (FIG. 3, Step Q).
9. Contact Hole Formation
A contact hole is selectively formed onto an interlayer insulating film through photolithography and etching (FIG. 3, Step R).
10. Metal Wiring Formation
A metal wiring is selectively formed on the interlayer insulating film through sputtering, photolithography, etching, etc. (FIG. 3, Step S).
11. Protective Film
A protective film is deposited on the metal wiring and an opening is selectively formed in a desired region (metal wiring in an external connection terminal region etc.) (FIG. 3, Step T).
12. Wafer Inspection
A semiconductor chip and an IC tester are electrically connected through a wafer prober to test electric characteristics etc. of the semiconductor device (FIG. 3, Step U).
As mentioned above, the semiconductor device is manufactured through a long-term manufacturing process. Looking closer, the manufacturing process is very complicated and consists of well over 100 steps.
The electric characteristics of the semiconductor device are determined depending on characteristics of circuit elements in the semiconductor chip. As well known in the art, the electric characteristic of a MOS transistor, which is a typical circuit element of the semiconductor device, is approximately represented by the following equation (1) for unsaturated state:Id=μC(W/L)(Vg−Vt)Vd  (1)where
Id: drain current of a transistor
μ: carrier mobility of the transistor
C: gate capacitance per unit area of the transistor
W: gate width of the transistor
L: gate length of the transistor
Vg: gate-source voltage of the transistor
Vd: drain-source voltage of the transistor
Vt: threshold voltage of the transistor
As apparent from the equation (1), the current characteristics of the transistor are determined by many characteristic parameters. Further, the threshold voltage Vt is derived from the following equation (2):Vt=VF+2.F+(QA+QB)/C  (2)where
VF: flat band voltage
F: shift in Fermi level due to impurity
QA: interface charge per unit area at an interface between the oxide film and the silicon surface
QB: charge per unit area of a depletion layer
C: gate capacitance per unit area of the transistor
The electric characteristics of the transistor manufactured through the manufacturing process including well over 100 steps may vary due to an influence of the long-term manufacturing process. In commercializing a semiconductor device, a product specification is determined by balancing the quality with the cost while taking the variations into account, and a circuit is designed such that the electric characteristics of the semiconductor device comply with the product specification. In some cases, however, high quality, e.g., high precision, should precede the cost as a result of reflecting the strong demand from the market. The characteristic parameter sensitive to the variations in electric characteristics, such as the threshold voltage Vt may largely vary between wafers, among the same lot, and in the same semiconductor chip as well as between lots. Heretofore, there is an increasing demand for realization of a manufacturing method which absorbs and lowers the variations of parameters having a large contribution to the variation in electric characteristics of the semiconductor device, such as the threshold voltage Vt.
Up to now, a manufacturing method for a semiconductor device has been proposed, with which the aforementioned problem is solved and the variations in the threshold voltage Vt are reduced. The manufacturing method is completed by adding, for example, a step of reducing variations of FIG. 14, to the typical manufacturing process flow of FIG. 2. The step of reducing the variations includes a quality check step F of measuring and checking a quality of a half-completed product in the middle of the manufacturing process, a condition setting step G of setting a manufacturing condition in a variation reduction step H included in the subsequent manufacturing process for the semiconductor device, based on the measurement information, and the variation reduction step H of absorbing and reducing the variations in electric characteristics under the set manufacturing condition for manufacturing the semiconductor device. The above three steps are regarded as being extended from the wafer inspection step (FIG. 3, Step U).
A first prior art aiming to solve the aforementioned problem provides a feed-back type manufacturing method including: measuring (or simulating) the threshold voltage Vt of an electronic element in a half-completed semiconductor chip during manufacture under existing manufacturing conditions; adjusting and determining the next manufacturing conditions for manufacturing the next lot based on the existing manufacturing conditions for the semiconductor device and the measurements; reducing variations in the threshold voltage Vt of the semiconductor device; and reducing variations in electric characteristics (see JP 2002-083958 A (p. 8, FIG. 1) for example). A second prior art aiming to solve the aforementioned problem provides a trimming type manufacturing method including: adjusting values (e.g., resistance value) of passive elements in a half-completed semiconductor chip; absorbing variations in the threshold voltage Vt etc. for each chip; and reducing variations in electric characteristics of a semiconductor device (see JP 07-086521 A (p. 5, FIG. 1), for example). These prior arts will be described in brief below, but detailed description will be referred to each publication.
The feed-back type manufacturing method as the conventional manufacturing method for the semiconductor device aimed to reduce production variations is a method of setting the next manufacturing condition based on the existing manufacturing condition of the manufacturing process in the case of manufacturing another semiconductor device. More specifically, it is a manufacturing method including: measuring the threshold voltage Vt of a semiconductor product manufactured under the existing manufacturing condition; measuring or evaluating a quality of the semiconductor device in course of manufacture (FIG. 15, Step F) and then revising and determining the next manufacturing condition based on the existing criteria (FIG. 15, Step G); and manufacturing the next semiconductor device under the next manufacturing condition (FIG. 15, Step H) to reduce the variations in electric characteristics of the semiconductor device. According to this feed-back type manufacturing method, the next manufacturing condition is adjusted based on information on current variations to thereby reduce the variations in electric characteristics of the semiconductor device. A specific method of determining the next manufacturing condition is shown in FIG. 15.
The trimming type manufacturing method as another typical manufacturing method for a semiconductor device aimed to reduce the production variation uses a trimming circuit as shown in FIG. 18. In the trimming circuit of FIG. 18, resistors 220 and 221 are electrically connected in series between external input terminals 300 and 301. Fuses 230 and 231 are connected to the resistors 220 and 221 in parallel, respectively. A gate electrode of a transistor 210 is connected to a node between the resistors 220 and 221. A drain region of the transistor 210 is connected to an external input/output terminal 303 through an internal circuit 240 while a source region thereof is connected to an external input/output terminal 304 through an internal circuit 241. The fuses 230 and 231 of the trimming circuit of this semiconductor device are formed of polysilicon but may be formed of aluminum etc. as a metal thin film. Note that, pairs of the resistors 220, 221 and of the fuses 230, 231 may be provided in plural as needed.
The trimming type manufacturing method includes: measuring and checking the quality of the half-completed semiconductor device midway through the manufacturing process (FIG. 16, Step F); and determining fuse cutout portions in the trimming circuit so as to absorb variations of individual semiconductor chips (FIG. 16, Step G) and trimming the individual semiconductor chips (FIG. 16, Step H) to thereby reduce the variations in electric characteristics of the semiconductor device.
However, the conventional manufacturing methods involve the following problems. With the feed-back type manufacturing method as the prior art of FIG. 15, initial conditions for new manufacturing process are first set by, for example, analogizing and referring from/to the existing manufacturing process (existing technique) and then a product is manufactured by way of trial or simulation through all the steps under the initial manufacturing conditions. Next, the quality is measured and checked, after which the initial manufacturing conditions are revised based on the preset criteria to determine the next manufacturing conditions. Thus, the quality check step F and the manufacturing condition setting step G cannot be applied to the semiconductor device in course of manufacture. The wafer inspection result of the completed semiconductor device can be fed back for improving the next manufacturing conditions to thereby improve the manufacturing process. However, this is not directly contributable to reduction in variations of the semiconductor device in course of manufacture.
With the trimming type manufacturing method as the prior art of FIG. 16, the half-completed semiconductor device itself is measured midway through the manufacturing process, and hence the quality check step F and the manufacturing condition setting step G can be applied to the semiconductor device in course of manufacture. However, in this method, quality damage is caused on the semiconductor device at the time of measurement (due to the contact type measurement in most cases) or a trimming circuit is provided in the semiconductor device for reflecting measurements therein in advance. As a result, this redundant circuit leads to an increase of chip area of the semiconductor device, resulting in lowering of mass-production efficiency and final increase in cost.